Blaze DFM Adds to Electrical DFM Lineup With Intelligent Fill Solution
Blaze IF provides “unbeatable” CMP fill synthesis results

Sunnyvale, Calif. – December 11, 2006 – Blaze DFM, the electrical DFM company, today announced that it is broadening its suite of electrical DFM products with the introduction of the Blaze IF™ fill synthesis tool. Blaze IF optimally meets complex CMP design rules without requiring complicated scripts, and without harming chip performance or power.

Blaze IF inserts “dummy” fill patterns into the design layout to reduce topographical variations that occur as a result of chemical mechanical polishing (CMP) during the manufacturing process. Failure to meet surface topography variation constraints causes defocus and pattern dimensional error in lithography, degraded transistor characteristics in the case of shallow trench isolation (STI), and electrical shorts or increased wire resistance in the case of metal interconnects, all of which are detrimental to circuit yield.

Blaze IF is based on the trailblazing fill synthesis research of University of California at San Diego professor Dr. Andrew B. Kahng, co-founder and chairman of Blaze. “The fill solutions produced by Blaze IF optimally meet foundry CMP rules,” said Dr. Kahng. “Blaze IF results are literally unbeatable – if there is a fill solution that meets foundry requirements, Blaze IF will find it, and the solution found by Blaze IF will be the best achievable.  On the other hand, if Blaze IF cannot find a feasible solution, then no solution exists.”

Motivation
Without Blaze IF, engineers must perform fill synthesis using custom scripts written for design rule verification tools. The advancing complexity of CMP design rules has caused fill insertion scripts to become overwhelmingly complex, to the point that it is impractical to maintain such an approach going forward (click here to view tutorial on fill synthesis).

As a tool specifically designed to handle advanced foundry CMP design rules, Blaze IF is much easier to maintain and use than the impractical “script-ware” being used today.  Blaze IF supports all modern CMP design rules, including allowed density upper and lower bounds, density smoothness constraints, dummy via insertion, dimension constraints and pattern types for dummies, dummy-to-dummy spacing, and spacing between dummies and functional trenches or wires, based on the planarity requirements for the inter-layer dielectric (ILD) overlying the metal.

Electrical DFM
Blaze DFM was the first to introduce a new generation of “electrical DFM” solutions with the announcement of the company and the release of Blaze MO leakage power optimization software in May 2006. Following in the footsteps of Blaze MO, Blaze IF uses a chip’s power and timing requirements to elevate fill to a level beyond the shape-centric approaches of the past. Blaze IF uses the Blaze timing and power analysis engines to maintain power and performance requirements while the fill shapes are being added. The result is that it ensures that foundry fill requirements are met while preserving timing correctness and minimizing the impact on dynamic power.

Silicon Validation
Blaze IF underwent extensive beta testing at a number of companies including Cypress Semiconductor. Cypress used Blaze IF to optimize the planarity of a high-speed sensor chip. The goal was to limit variations in inter-layer dielectric thickness to 30%. The actual result achieved was 13%. The results were first verified through CMP simulation, and then validated in silicon.

“Blaze IF offers a number of advanced fill synthesis techniques that we require for our leading-edge devices,” said Dr. Artur Balasinski, Principal Engineer at Cypress. “We worked together with the Blaze engineers to validate Blaze IF results in silicon on a product chip and they exceeded our expectations by a wide margin.”

Features
Blaze IF includes the following features:

• Performs multi-layer, multi-window global optimization of effective density smoothness and uniformity
• Optimizes fill on all layers simultaneously
• Assured to meet design rules if any feasible solution exists
• Meets all modern constraint types – completely design rule compliant
• Maintains electrical correctness during fill using internal delay calculation, timing analysis, signal integrity analysis and power analysis engines
• Includes advanced solutions for hard IP integration and automatic analog fill for complete SOC support
• Provides solution for all layers – STI, poly, via and metal
• Offers a flexible set of fill strategies including floating, grounded and track fill
• Supports standalone, ECO and ripup-refill use models
• “Dual mode” capability supports model-based fill synthesis using foundry-supplied topography modeling engines as well as traditional rule-based fill synthesis

Availability
Blaze IF is available immediately on 32-bit and 64-bit Red Hat Linux and 64-bit SUSE Linux. List pricing starts at $250,000 per year.

About Blaze DFM
Blaze DFM provides software solutions to fabless semiconductor companies, integrated device manufacturers, and silicon foundries. Blaze products give IC designers greater control over manufacturing variability, improving yield and shortening time to volume production. Blaze DFM, Inc., 1275 Orleans Drive, Sunnyvale, CA 94089, 408.470.4900. Web: http://www.blaze-dfm.com
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