 |
 |
       |
Articles  Press Releases |
 |
 Blaze DFM Qualified by STARC for 65nm Leakage Power Optimization Sunnyvale, Calif. – January 22, 2007 – Blaze DFM, the electrical DFM company, has been chosen by the Semiconductor Technology Academic Research Center (STARC) to provide leakage power optimization software that will be integrated into the STARCAD-CEL (Certified Engineering Linkage, one step ahead of DFM) reference design methodology. With this methodology, STARC - Japan's leading semiconductor technology research organization supported by Japanese IDMs - is targeting the establishment of a process-friendly and low-power reference flow that strives to eliminate manufacturing uncertainty in 45nm-32nm system LSI designs. As part of the qualification process, STARC performed a detailed evaluation of the Blaze MO leakage optimization solution using a three million gate, 65nm chip. Blaze MO employs two complementary techniques for leakage power reduction – transistor gate length biasing and threshold voltage (Vt) assignment. First, they created a baseline design using their standard STARCAD-CEL design methodology. Then, they optimized the design using Blaze MO’s patented gate length biasing capability. Subthreshold leakage power in the Blaze-optimized design was 45% lower than in the baseline design. Next, they re-optimized the design with Blaze MO for both leakage power and timing using gate length biasing and Vt assignment with multi-Vt libraries. Leakage power was 36 % lower and timing was 30% faster than the original baseline design. “For many of our member companies, power has become the most critical yield-limiting factor for their designs,” said Nobuyuki Nishiguchi, vice-president and general manager at STARC. “A reduction in leakage power of this magnitude, in addition to what is already achievable using more conventional techniques, adds significant value to any design flow for 65nm or below.” Blaze MO uses a design’s power and timing requirements to drive the manufacturing process. This results in significant improvements in leakage power, leakage variability, and timing. Blaze MO tailors the manufacturing process for each individual design by providing design-specific guidance to the design-to-mask flow, so the chip designer is assured of realizing the full potential from advanced processes. Blaze MO has been proven on 90nm and 65nm customer designs to reduce leakage power by more than 40% and leakage variability by up to 60% and to improve timing by 10% or more. Blaze MO does not require chip designers to become manufacturing experts, nor does it change the handoff to manufacturing. Blaze MO works with existing process information that is already available in standard design kits. Blaze MO reads and writes industry standard file formats and can be plugged into existing design flows. Unlike DFM tools that only provide analysis capabilities, Blaze MO also provides optimization capabilities that improve parametric yield. This increases the number of chips on each wafer that meet power and timing specifications across the process window. The value of Blaze MO has been proven in silicon and validated on production designs at a number of top-tier IDMs, fabless semiconductor companies, and foundries. “STARC’s endorsement of Blaze MO is of great strategic importance because all of the member companies will be presented with the results of their evaluation,” said Jacob Jacobsson, president and CEO at Blaze. “STARC plays a key role in identifying and qualifying new technologies for their consortium members and we’re looking forward to working with them to address the critical design challenges at 65nm and below.” Blaze MO will be featured in the Itochu Techno-Solutions Corporation (booth #104) and STARC (booth #606) exhibits at the Electronic Design and Solution Fair 2007 at the Pacifico Yokohama, Japan, on January 25-26, 2007. About Blaze MO About Blaze DFM
|
|
 |
