Blaze IF is a dedicated fill synthesis solution designed to meet the most stringent density and smoothness requirements of advanced process technologies. Blaze IF inserts “dummy” fill patterns into the layout to reduce topographical variations that occur as a result of chemical mechanical polishing (CMP) during the manufacturing process.

Blaze IF enables designers to:
• Minimize thickness variations in a multi-layer metal stack
• Preserve timing and power integrity on critical nets
• Synthesize fill for all layers – STI, poly, via and metal

Blaze IF will find an optimal fill solution, if one exists. It performs multi-pass, multi-window fill synthesis optimizing the planarity of all layers simultaneously. It has built-in analysis engines to ensure that the inserted fill shapes do not adversely affect the timing and power characteristics of the chip. Blaze IF provides a complete fill solution for SoC designs, including full support for variable pitch layers, analog circuitry, and hard IP blocks.

Enhanced Planarity for Greater Parametric Yield
Failure to meet topography variation constraints causes defocus and pattern dimensional error in lithography, degraded transistor characteristics in the case of shallow trench isolation (STI), and electrical shorts or increased wire resistance in the case of metal interconnects, all of which are detrimental to circuit yield.

Variations in layer thickness can cause both functional and parametric failures (failure to meet timing and power requirements). At advanced sub-100nm process nodes, parametric failures are the dominant cause of chip failure. Thickness variations are cumulative in that the planarity of any given layer directly affects the layers above. Fill insertion acts to reduce variations in layer thickness resulting in smoother surfaces and fewer parametric failures.

Without Blaze IF, fill insertion must be performed after design closure by physical verification tools that are driven by geometric design rules and density targets. However, this approach is rapidly running out of steam in advanced technology nodes. In addition, it does not take into consideration the effect of fill shapes on the timing and power characteristics of the design. Fill shapes placed close to timing-critical nets can result in excessive coupling capacitance. Fill shapes placed close to highly active switching nets can result in increased power dissipation. Above 100nm, these electrical effects are negligible, but below 100nm, they can cause parametric failures.

Blaze IF is fully aware of timing and power requirements and optimizes planarity without adversely affecting timing and power. Silicon-validated results show that Blaze IF can reduce variations in inter-layer dielectric thickness by more than 50%.

Design Flow Integration
Blaze IF is built on the Open Access database. It integrates easily into existing design flows from Cadence, Synopsys and Magma using industry standard file formats, including SDC, Liberty, Verilog, LEF/DEF, DSPF/SPEF, VCD and GDSII.

Blaze IF fits into the design flow directly before handoff to manufacturing.

Users interact with Blaze IF through Tcl scripts or the graphical user interface.