Reduce leakage power by 20% or more. Cut leakage variability in half.

You may believe that you are already doing everything possible to reduce leakage power by using:
multi-Vt libraries, header/footer sleep switches, voltage islands, transistor body biasing.

We can help you to reduce leakage power even more. Blaze MO offers the following benefits:

• Reduce leakage power by 20% or more on digital CMOS designs
• Cut leakage variability in half
• No performance hit
• No schedule hit
• Guaranteed timing closure
• Can be used on existing or in-process designs
• No change to architecture, libraries, logic design, or layout
• Fully compatible with, and additive to, the leakage reduction techniques mentioned above
• Plugs into any existing design flow
• Only one mask (poly) is affected
• Supported by major foundries

Please contact us for more information on how you can reduce leakage power on your designs today.

Here are some customer-written articles on how they are reducing leakage power with Blaze MO.

Article: Leakage Power Optimization for a Wireless Comms SoC, EDA Tech Forum 12/06
Article: Leakage reduction in SOCs using gate-length biasing, Solid State Technology 9/06
Article: Leakage Power Reduction in a Mobile Baseband Processor, Chip Design 7/17/06