Electrical DFM solutions address the issue of parametric yield for integrated circuits implemented with sub-100nm process technologies. Electrical DFM tools give chip designers control over manufacturing issues that cause parametric failures (chips that don’t meet timing or power requirements).

There are three precepts that define electrical DFM solutions. They: 1) drive design requirements forward into manufacturing, 2) bring manufacturing awareness upstream into design, and 3) do not require any major disruptive changes to the design flow, design-to-manufacturing handoff, or to the fab equipment line.

In electrical DFM, “design requirements” explicitly refers to timing and power (electrical) requirements, not just geometric information. Bringing design requirements forward into manufacturing means using the actual timing and power constraints supplied by the design team to drive what happens in manufacturing. Typically, this is done by interfacing with the resolution enhancement technology (RET) process in manufacturing. However, other manufacturing interactions can also provide beneficial results.

Bringing manufacturing awareness into design requires modeling systematic sources of within-die and die-to-die variation. Although having a detailed model of the process can be desirable, such models are not yet commonly available. However, many important sources of variation can be accounted for using an a priori understanding of process technology. Accounting for these variation sources can remove a great deal of uncertainty during design without requiring foundries to supply proprietary information.

To be useful, electrical DFM solutions must be practical for designers to adopt and use. They must be based on open standards, should not require design flow changes, and should work with the existing “golden” standard tools used for verification and OPC.